High speed bus transceiver with fault tolerant design for...

H - Electricity – 04 – B

Patent

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H04B 1/40 (2006.01)

Patent

CA 2178846

A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

L'invention est un système de transmission de données rapide pour ordinateurs, commutateurs, microprocesseurs et entités similaires qui comprend un bus différentiel à faible impédance et une pluralité d'émetteurs-récepteurs connectés à ce bus. Chacun de ces émetteurs-récepteurs est doté d'un circuit d'attaque qui transfère les données sur le bus et d'un récepteur qui reçoit les données transmises par le bus. Le circuit d'attaque comprend un circuit pseudodifférentiel qui absorbe le courant dans l'un des branchements du bus différentiel seulement sans perturber l'autre branchement. Le récepteur comprend un comparateur différentiel polarisé à une tension de sortie réglable.

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