High speed bus transceiver with fault tolerant design for...

Details High speed bus transceiver with fault tolerant design for... High speed bus transceiver with fault tolerant design for...

H - Electricity

03

K

H03K 19/082 (2006.01) G06F 13/40 (2006.01) H03K 19/0175 (2006.01) H04L 25/08 (2006.01)

Patent

CA 2073105

A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.

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