High speed cache miss prediction method and apparatus

Details High speed cache miss prediction method and apparatus High speed cache miss prediction method and apparatus

G - Physics

06

F

G06F 13/20 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2121221

In a data processing system which employs a cache memory feature, a method and exemplary special purpose apparatus for practicing the method are disclosed to lower the cache miss ratio for called operands. Recent cache misses are stored in a first in, first out miss stack, and the stored addresses are searched for displacement patterns thereamong. Any detected pattern is then employed to predict a succeeding cache miss by prefetching from main memory the signal identified by the predictive address. The apparatus for performing this task is preferably hard wired for speed purposes and includes subtraction circuits for evaluating variously displaced addresses in the miss stack and comparator circuits for determining if the outputs from at least two subtraction circuits are the same indicating a pattern yielding information which can be combined with an address in the stack to develop a predictive address. The efficiency of the method and apparatus is improved by providing pattern detection logic circuitry for searching for a plurality of patterns simultaneously and priority logic circuitry which establishes precedence in the event that more than one pattern is sensed with a given set of recent cache misses.

Affiliated with

Also associated with

Rating

High speed cache miss prediction method and apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed cache miss prediction method and apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed cache miss prediction method and apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1609469