High speed data transfer for a semiconductor memory

Details High speed data transfer for a semiconductor memory High speed data transfer for a semiconductor memory

G - Physics

11

C

352/40

G11C 11/34 (2006.01) G11C 7/10 (2006.01) G11C 8/04 (2006.01) G11C 8/10 (2006.01)

Patent

CA 1161956

HIGH SPEED DATA TRANSFER FOR A SEMICONDUCTOR MEMORY ABSTRACT OF THE DISCLOSURE A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for stor- ing data derived from successive locations in memory, and a corresponding plurality of serially coupled decoders, each associated with one of the data latches In response to an address input, one decoder is enabled for causing its associated data latch to output its stored data to the data buss. The latter decoder then disables itself and enables the next decoder so that a second latch out- puts its stored data. The process continues with each de- coder disabling itself and enabling the next decoder so that the data latches are caused to sequentially output their stored data.

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