High-speed demultiplexer circuit

Details High-speed demultiplexer circuit High-speed demultiplexer circuit

H - Electricity

04

J

363/17

H04J 3/04 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1299784

-18- A HIGH-SPEED DEMULTIPLEXER CIRCUIT Abstract A demultiplexer for demultiplexing a multiplexed input data signal into M output channels using M sequencer means clocked from an overlapping M phase system clock. The system clock operates at a frequency equal to the input data signal rate divided by M. Each sequencer means is clocked by a unique combination of the M phase system clock signals to select one data channel from the multiplexed input data signal. Since all sequencer means circuits are synchronized to the system clock, no variable delay lines are needed to align the timing between the circuit stages. A time delay latch is provided where needed in each sequencer means to enable all channels to output data concurrently. The demultiplexer includes a real-time data-framing capability to assure that the input data is correctly mapped to the proper output channels.

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