High speed dynamic binary incrementer

Details High speed dynamic binary incrementer High speed dynamic binary incrementer

G - Physics

06

M

G06M 1/00 (2006.01) G06F 7/50 (2006.01)

Patent

CA 2155380

A high speed dynamic binary incrementer is provided that requires only two stages regardless of the bit width of the incrementer. The binary incrementer utilizes the inverse of logical carry expressions to provide for a first stage. A sum stage receives the inverted carry and the input signals to provide the incremented value. Dynamic wired OR Logic is utilized advantageously to provide the dynamic binary incrementer.

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