High speed ecl input buffer for vertical fuse arrays

Details High speed ecl input buffer for vertical fuse arrays High speed ecl input buffer for vertical fuse arrays

H - Electricity

03

K

328/126

H03K 19/177 (2006.01) G11C 8/08 (2006.01) G11C 17/16 (2006.01) H03K 19/00 (2006.01) H03K 19/018 (2006.01)

Patent

CA 1318367

27008/NSCO-5 A HIGH SPEED ECL INPUT BUFFER FOR VERTICAL, FUSE ARRAYS ABSTRACT OF THE DISCLOSURE An ECL input buffer is particularly well- suited for use with logic arrays where a large amount of current must be sunk by the row line, for example, when vertical fuse devices are used in an AND array. The input buffer provides means for pulling down the row line such that the entire amount of current sunk by the input buffer from the row line need not pass through a current source, thereby minimizing current consumption of the input buffer. A pull down current source is used which causes a pull down transistor to turn on, thereby pulling down the row line while requiring only the base current of the pull down transistor to be consumed by the current source. A pull up device is utilized and means are included for insuring that the pull up and pull down devices are not both turned on simultane- ously, thereby preventing a current spike through the pull up and pull down means. APP:27008

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