High speed, flexible source/destination data burst direct...

Details High speed, flexible source/destination data burst direct... High speed, flexible source/destination data burst direct...

G - Physics

06

F

G06F 13/28 (2006.01)

Patent

CA 2074506

2074506 9111767 PCTABS00006 A direct memory access control system (2120) provides for the high speed burst transfer of data blocks from a data source to a data destination. The system includes a first processor (2100) for identifying one or more data blocks for transfer from a data source to a data destination and prepares a data structure defining the data transfer required for the transfer of the data block. A second processor (2160) responsive to an enable signal, autonomously generates addressing signals and data transfer signals to effect the transfer of a data block from the data source to the data destination. Upon completion of a transfer, the second processor (2160) generates a transfer done signal. A third processor (2170) responsive to the first processor is provided to initialize the second processor for the transfer of a data block determined by the defining data structure as prepared by the first processor.

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