High speed high density dynamic address translator

Details High speed high density dynamic address translator High speed high density dynamic address translator

G - Physics

11

C

354/239

G11C 11/407 (2006.01) G06F 12/10 (2006.01) G11C 15/04 (2006.01)

Patent

CA 1293332

ABSTRACT OF THE DISCLOSURE A translator is organized to include at least a pair of content addressable memories (CAMs), each for storing a different portion of the total number of bits of each of the words to be translated. The outputs from each CAM are logically combined within a multiple input random access memory (RAM). Both CAMs are interrogated simultaneously and deliver the results of comparing the word portions of an input word and the CAM contents to the RAM in substantially less time than required for a single CAM memory. The results are logically combined within the RAM which, in response to a match condition, delivers the results of the translation as an output.

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