High speed, high yield cmos/sos process

Details High speed, high yield cmos/sos process High speed, high yield cmos/sos process

H - Electricity

01

L

356/125

H01L 21/265 (2006.01) H01L 21/033 (2006.01) H01L 21/86 (2006.01) H01L 27/12 (2006.01)

Patent

CA 1048654

HIGH SPEED HIGH YIELD CMOS/SOS PROCESS Abstract of the Disclosure The specification discloses a high speed, high yield process for the production of complementary metal-oxide semiconductor devices in silicon on sapphire (CMOS/SOS devices). The process involves providing a wafer comprising a layer of silicon on a sapphire substrate, forming the silicon into several independent islands, masking selected portions of the islands, applying a material to alter the conductivity of the unmasked portions, oxidizing the islands, applying a silicon nitride layer over the surface of the substrate and islands, masking portions of the nitride layer and etching unmasked portions as well as the unmasked oxide layer, applying a second material to the unmasked portions in order to alter the conductivity of the unmasked portions of the islands, oxidizing the islands, selectively masking and etching portions of the oxidized islands, and applying conductors to the exposed portions of the silicon islands to function as contacts. This process yields low resistance n-type silicon regions where desired, while providing high yield and high speed production.

243794

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