High speed logic and memory family using ring segment buffer

Details High speed logic and memory family using ring segment buffer High speed logic and memory family using ring segment buffer

H - Electricity

03

K

H03K 5/13 (2006.01) H03K 3/03 (2006.01) H03K 3/356 (2006.01) H03K 17/567 (2006.01) H03K 19/017 (2006.01) H03K 19/0175 (2006.01) H03K 19/0944 (2006.01) H03K 19/0948 (2006.01) H01L 27/07 (2006.01) H01L 27/118 (2006.01)

Patent

CA 2078778

A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages. For large capacitive loads, the last stage of the Ring Segment Buffer may be replaced by a bipolar transistor-FET driver in which minority carrier lifetime controlled bipolar transistors are used. For logic applications, a Ring Segment Buffer couples each logic gate on a chip to its capacitive load to thereby provide Buffer Cell Logic. Each Ring Segment Buffer is designed to couple the logic gate to its individual capacitive load, while preserving the desired logic chip speed. For memory applications, a memory cell may be coupled to a Ring Segment Buffer which is designed to drive the memory cell's capacitive load at the desired memory chip speed, and also to provide a desired signal delay. Such a Delay Storage cell may be used to design a shift register or binary counter which only requires one clock pulse for operation, because the delay of the Ring Segment Buffer allows internal clocking. The Delay Storage cell may also be used to design a multivibrator, clock generator and other circuits which operate high speed using only one clock pulse. The Buffer Cell Logic and Delay Storage technology of the present invention may operate at speeds of 300 megahertz or more using conventional semiconductor fabrication processes in which conventional CMOS logic and memory technology operates at 70 megahertz or less. A fourfold speed improvement is thereby obtained.

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