High speed low pin count bus interface

Details High speed low pin count bus interface High speed low pin count bus interface

G - Physics

06

F

354/232

G06F 13/40 (2006.01)

Patent

CA 1297197

HIGH SPEED LOW PIN COUNT BUS INTERFACE ABSTRACT Bus interface apparatus is provided to drive a high speed bus with two nonoverlapping clock signals. The apparatus takes advantage of the inherent bus capacitance which will tem- porarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals.

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