High speed merged charge memory

Details High speed merged charge memory High speed merged charge memory

G - Physics

11

C

352/82.4

G11C 11/24 (2006.01) G11C 11/404 (2006.01) G11C 11/408 (2006.01) H01L 27/108 (2006.01)

Patent

CA 1231445

HIGH SPEED MERGED CHARGE MEMORY ABSTRACT A semiconductor memory produced in a unipolar technology includes a cell which has a diffusion storage capacitor with one overlying terminal being merged with a bit/sense line, the other capacitor terminal is a diffused region and is coupled through a word transfer device to a word line injector charge source held at a fixed voltage. To provide an organ- ized array of these cells, each bit line cell includes a shared word line charge source held at a fixed voltage and formed at the surface of a semiconductor substrate. A diffusion storage capacitor also is formed at the surface of the semiconductor and spaced apart from the shared charge source. Information is written into each bit line capacitor by applying a voltage of either of two different magnitudes, repre- senting 1 and 0 bits of information, to the respective bit line while a word selection pulse produces an inversion layer at the surface of the substrate between each bit line capacitor and its shared word line fixed voltage charge source. At the termination of the word pulse, the fixed voltage remains stored at the capacitor node. The capacitors having the larger voltage applied to the bit line terminal of the capacitors store the greater amount of charge. This charge can then be detected by measuring the voltage of the floating bit sense line when a word pulse again connects the fixed voltage charge source with each of its respective capacitors.

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