High-speed multiplexer circuit

Details High-speed multiplexer circuit High-speed multiplexer circuit

H - Electricity

04

J

363/17

H04J 3/04 (2006.01) H04L 7/033 (2006.01)

Patent

CA 1300769

- 16- A HIGH-SPEED MULTIPLEXER CIRCUIT Abstract A high data rate multiplexer (MUX) architecture includes front- end and rear-end MUXs clocked at a system clock rate equal to one-half of the MUX output data rate. The front-end MUX selects inputs under control of select signals derived from multiple phases of a select clock. The select clock is derived from the system clock. The number of select signals is equal to the multiplexing factor of the MUX.

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