High speed parallel multiplier circuit

Details High speed parallel multiplier circuit High speed parallel multiplier circuit

G - Physics

06

F

354/182

G06F 7/52 (2006.01)

Patent

CA 1295743

ABSTRACT OF THE DISCLOSURE The binary multiplier circuit for obtaining a product of a M-bit multiplier and a N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit, In the ma- trix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most signifi- cant bit position. For every column having three or fewer oriqi- nal summand bits, and having the least significant column posi- tion that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most sig- nificant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any re- maining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits. The remaining two rows of bits can be input to a carry-propaga- ting adder circuit to output a sum equal to the product.

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