High speed parallel multiplier circuit

Details High speed parallel multiplier circuit High speed parallel multiplier circuit

G - Physics

06

F

354/182

G06F 7/52 (2006.01)

Patent

CA 2015706

ABSTRACT OF THE DISCLOSURE The binary multiplier circuit for obtaining a product of an M-bit multiplier and an N-bit multiplicand includes a mul- tiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the col- umn in the next most significant bit position. For every column having three or fewer original summand bits, and hav- ing the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most signifi- cant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits. The remaining two rows of bits can be input to a two-stage carry-propagating adder circuit to output a sum equal to the product.

Affiliated with

Also associated with

Rating

High speed parallel multiplier circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed parallel multiplier circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed parallel multiplier circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1525809