High speed processor for digital signal processing

Details High speed processor for digital signal processing High speed processor for digital signal processing

G - Physics

06

F

354/167

G06F 7/52 (2006.01) G06F 7/00 (2006.01) G06F 9/38 (2006.01) G06F 15/78 (2006.01) G06T 17/00 (2006.01)

Patent

CA 2038822

ABSTRACT OF THE DISCLOSURE HIGH SPEED PROCESSOR FOR DIGITAL SIGNAL PROCESSING A high speed processor (HSP) including a processor interface (106), an output pipeline (212) interface, an input pipeline (214) interface, and a multichip floating point processor (110). The floating point processor (110) further comprises a data register (200) file memory, a coefficient register (204) file memory, a floating point multiplier-accumulator (201), a microsequencer (206) and a control store (208) random access memory (RAM). The high speed processor provided by the present invention is capable of operating at a clock rate of about 200MHz with the floating point processor capable of 400 MFLOPS peak performance. In one embodiment of the invention, the HSP is entirely self contained in a TFML package with all high speed interfaces residing on the package substrate and only C-MOS speed interfaces residing off of the FPP package. The FPP comprises five GaAs integrated circuit consisting of a floating point multiplier-accumulator (201) (MACC), a plurality of multi-port register file memories (RFM), RAM for microprogram storage and a clock generator.

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