High-speed programmable packet scheduler and buffer manager

H - Electricity – 04 – L

Patent

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Details

H04L 12/56 (2006.01) H04L 12/24 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2290265

A method and apparatus for managing the buffering and for scheduling the transfer of packets of data arriving on one or a plurality of input ports and destined for one or a plurality of output ports of a packet switch or router or a subsystem thereof is disclosed. Each arriving packet is assigned an index that specifies both a unique destination output port for the packet and membership in a subclass, such as a priority class, a connection or flow, or a class of packets that is to receive a certain type of transmission or buffering service. For each arriving packet, a minipacket is created that contains the index of the packet, a unique identifier such as a storage location, and optionally information relevant to the scheduling and buffering of the packet. Each index is assigned a unique queue in which minipackets with the given index are placed in order of arrival. A method and apparatus for a scheduler and buffer manager is disclosed that: maintains a large number of said queues; identifies the head-of line minipackets from said queues to a head-of line sequencer ; selects the order in which minipackets are output according to a scheduling algorithm. Packets are transmitted from storage to output ports according to the sequence of minipackets that exit the scheduler system. The disclosed scheduler is flexible and can be programmed to implement various scheduling algorithms, including weighted fair queuing, priority queuing, hierarchical fair queuing and all variations that involve sorting according to a tag value. The disclosed scheduler is scalable in that it can provide individual queues for a very large number of port/subclass combinations. The disclosed scheduler can be implemented in integrated circuits to operate at very high speeds.

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