High speed scrambling at lower clock speeds

Details High speed scrambling at lower clock speeds High speed scrambling at lower clock speeds

H - Electricity

04

J

363/10

H04J 3/02 (2006.01) H04J 3/04 (2006.01) H04L 25/03 (2006.01) H04J 14/08 (2006.01)

Patent

CA 1283229

Abstract of the Disclosure Circuitry generates a plurality of differently- phase ?-sequences (or pseudo-random sequences) for scrambling/descrambling of all tributary data signals at a multiplexer/demultiplexer. By scrambling/descrambling at the tributary levels and thus at the lower tributary clock rates, less complex circuitry can be employed, and by properly selecting the tributary scrambling sequences in accordance with the teachings of this invention, a desired high speed line sequence can be attained.

568576

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