High-speed sequential adder

G - Physics – 06 – F

Patent

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354/204

G06F 7/50 (2006.01) G06F 7/60 (2006.01)

Patent

CA 1158774

ABSTRACT OF THE DISCLOSURE The words to be added together by the high- speed sequential adder are stored in shift registers whose serial outputs are connected to the corresponding inputs of a transcoder producing the binary number of "1's" for each bit weight of the words to be added. This value is sent to an adder-divider which adds it to the number of carried "1's" from the immediately lesser weight and divides this sum by 2, sending the fractional part of this half-sum to an output register and the whole-number part to a carry register. Application: digital filters for PCM telephone switching.

349541

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