High speed synchronous computer

Details High speed synchronous computer High speed synchronous computer

G - Physics

06

F

354/230.81

G06F 9/00 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1145478

NIX-105 HIGH-SPEED SYNCHRONOUS COMPUTER ABSTRACT A digital processor including both macro and micro instruction generators. The micro-instruction generator comprises a sequencer for generating instruc- tion addresses, a memory for generating instructions in response to the addresses and a pipeline register adapted to receive the instructions for execution. The sequencer operates at a constant CLK 1 rate while the pipeline register operates at a variable CLK 2 rate; i.e., the occurrence of a branch instruction in the pipeline register operates to inhibit CLK 2 for one CLK 1 time so as to prevent loading for execution of the aborted sequential instruction during the loading of a new non-sequential instruction address. CLK 2 resumes upon the next CLK 1 signal to resume sequential opera- tion. Special branch instructions are utilized to fetch macro-instructions from a pipelined system of macro- instruction registers. A two-tier synchronous arbitra- tion system for memory requests is also disclosed.

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