High-speed synchronous counter circuitry

Details High-speed synchronous counter circuitry High-speed synchronous counter circuitry

G - Physics

06

M

G06M 1/00 (2006.01) H03K 23/50 (2006.01)

Patent

CA 2175614

Digital counter register stages RCRG(N) are constructed as two- to-one mux registers, each employing a multiplexer stage (113) having first, second, and third inputs (S0, I0, I1) and an output (116) connected to the switching signal input (D) of a D-type flip-flop (15), whose Q output comprises a first input (I1) to the multiplexer stage (113). An inverter buffer (19) is associated with each register stage (RCRG(N)) and has an input connected to the output (Q) of said D-type flip-flop (115) and an output connected to the second input (I0) of the multiplexer stage (RCRG(N)) and fed forward to a NOR gate (21) associated with each subsequent register stage (RCRG(N)).

Affiliated with

Also associated with

Rating

High-speed synchronous counter circuitry does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High-speed synchronous counter circuitry, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High-speed synchronous counter circuitry will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1568477