High voltage dielectrically isolated dual gate solid-state...

Details High voltage dielectrically isolated dual gate solid-state... High voltage dielectrically isolated dual gate solid-state...

H - Electricity

01

L

356/161, 356/34

H01L 29/06 (2006.01) H01L 21/762 (2006.01) H01L 29/739 (2006.01)

Patent

CA 1123122

Abstract of the Disclosure The present invention relates to a structure comprising a semiconductor body whose bulk is of one conductivity type and which has a major surface, a localized first region which is of the one conductivity type, and a localized second region and a localized third region which are both of the opposite conductivity type. Each of the localized first, second and third regions are of relatively low resistivity as compared to the bulk portion of the semiconductor body and are spaced apart from the others. Separate electrodes are connected to each of the first, second and third regions The localized first, second and third regions each have a portion thereof which forms a part of the major surface. The semiconductor body is separated from a semiconductor wafer (substrate) by a dielectric layer. The semiconductor wafer (substrate) is adapted to facilitate connection to an electrode and is characterized by a localized fourth layer of the same conductivity type as the third region. The fourth layer is sandwiched between the dielectric layer and the semiconductor body.

340787

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