High voltage protection circuit on standard cmos process

Details High voltage protection circuit on standard cmos process High voltage protection circuit on standard cmos process

H - Electricity

03

K

H03K 19/0948 (2006.01) H01L 27/02 (2006.01) H01L 27/06 (2006.01) H03K 17/10 (2006.01) H03K 19/003 (2006.01)

Patent

CA 2377896

There is disclosed a circuit topology for avoiding transistor gate oxide- dielectric breakdown and hot-carrier degradation in circuits, such as CMOS inverters, fabricated in a standard sub-micron CMOS process with feature size below 0.8 µm and gate-oxide thickness less than 150 .ANG.. An inverter circuit according to the invention incorporates transistors M6, M2, M3, M5 appropriately biased, additional to those of a standard inverter circuit (comprising M1 and M4), in order to avoid hot-carrier degradation and gate- oxide breakdown of M4 and M1. The invention is also applicable to transistor circuits having other functionalities for example logic level translators.

L'invention concerne une topologie de circuit permettant d'éviter les claquages du diélectrique d'oxyde de grille du transistor et la dégradation provoquée par la chaleur des supports dans des circuits, tels que des inverseurs CMOS, fabriqués dans des processus CMOS normalisés inférieurs au micron, dont la dimension caractéristique est inférieure à 0,8 µm et l'épaisseur de l'oxyde de grille inférieure à 150 .ANG.. Selon l'invention, un circuit inverseur incorpore des transistors M6, M2, M3, M5 polarisés de façon appropriée, en plus de ceux d'un circuit inverseur normalisé (comprenant M1 et M4), de manière à éviter la dégradation provoquée par la chaleur et le claquage de l'oxyde de grille de M4 et M1. Elle concerne également des circuits transistorisés possédant d'autres fonctions, tels que, par exemple, des translateurs de niveaux logiques.

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