Highly integrated, high-speed memory with bipolar transistors

Details Highly integrated, high-speed memory with bipolar transistors Highly integrated, high-speed memory with bipolar transistors

G - Physics

11

C

352/82

G11C 7/00 (2006.01) G11C 11/40 (2006.01) G11C 11/411 (2006.01) H01L 27/102 (2006.01)

Patent

CA 1182218

HIGHLY INTEGRATED HIGH-SPEED MEMORY WITH BIPOLAR TRANSISTORS Abstract A memory is described comprising a static MTL memory cell for high speeds, wherein the cell or pri- mary injectors (Pl, Pl') and the bit line injectors (P4 and P5) are coupled to each other by angular in- jection coupling via the low-resistivity base region of the flip-flop transistors (T2 and T3) of the memory cell. Such a memory cell has a structure with a low-resistivity signal path in the current flow area. The density is additionally increased by the primary injectors and the bit line injectors of adjacent cells of the array being used in common several times at a very high read signal.

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