Highly pipelined bus architecture

Details Highly pipelined bus architecture Highly pipelined bus architecture

G - Physics

06

F

G06F 13/42 (2006.01) G06F 12/08 (2006.01) G06F 13/18 (2006.01)

Patent

CA 2181704

A computer system (15), as shown , incorporating a pipelined bus (20) that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system (15) includes bus agents (2, 4, 6, 8, 10, 12, 14) having in-order queues (100) that track multiple outstanding transactions across a system bus (20) and that perform snops in response to transaction request, providing snoop results and modified data within one transaction. Additionally, the system (15) supports long latency transactions by providing deferred identifiers during transaction requests that are used to restart deferred transactions.

On décrit un système d'ordinateur comprenant un bus pour un traitement en cascade qui maintient la cohérence des données, qui permet des transactions avec une latence prolongée et qui assure l'ordre correct du traitement. Le système d'ordinateur comporte des agents de bus qui ont des files d'attente ordonnées pour effectuer des transactions multiples en attente, via un système de bus et qui effectuent des écoutes en réponse aux demandes de transactions, en fournissant les résultats de l'écoute et des données modifiées à l'intérieur d'une transaction. En outre, le système permet des transactions avec une latence prolongée en fournissant des identificateurs différés durant les demandes de transaction qui sont utilisés pour redémarrer les transactions différées.

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