Hitless clock recovery in atm networks

Details Hitless clock recovery in atm networks Hitless clock recovery in atm networks

H - Electricity

04

L

H04L 7/033 (2006.01) H03L 7/14 (2006.01) H04L 12/56 (2006.01) H04J 3/06 (2006.01)

Patent

CA 2184013

A method of generating timing signals for constant bit rate data received over an asynchronous data network carrying, comprises recovering clock signals from at least two separate sources, selecting one of the sources to drive a phase-locked loop generating a high speed output signal locked to the selected source, dividing the high speed output signal to provide the required timing signals for said constant bit rate data, and continually monitoring the selected source. In the event of failure of the selected source, the phase-locked loop is allowed to free run in a hold-over mode while it is switched over to the other source.

L'invention est une méthode de génération de signaux d'horloge pour des données à débit binaire constant reçues via un réseau de transmission de données asynchrone. La méthode de l'invention comporte les opérations suivantes : recouvrement des signaux d'horloge provenant de deux sources distinctes au moins, sélection de l'une des sources pour attaquer une boucle à asservissement de phase qui produit un signal à grand débit asservi à la source choisie, division de ce signal à grand débit pour obtenir les signaux d'horloge requis par lesdites données à débit binaire constant, et surveillance continue de la source choisie. En cas de défaillance de la source choisie, la boucle à asservissement de phase est autorisée à fonctionner librement en mode de maintien pendant sa commutation à l'autre source.

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