Hot-carrier suppressed sub-micron misfet device

Details Hot-carrier suppressed sub-micron misfet device Hot-carrier suppressed sub-micron misfet device

H - Electricity

01

L

H01L 21/336 (2006.01) H01L 29/08 (2006.01) H01L 29/78 (2006.01)

Patent

CA 2065242

2065242 9104577 PCTABS00003 Hot-carrier suppression in a sub-micron MISFET structure is achieved by providing a drain region which includes a steeply profiled N+ (or P+) doped region (34) in the surface of a semiconductor body (30) with a first epitaxial layer (44) formed thereover having N- (or P-) dopant concentration. A second N+ (or P+) epitaxial layer (48) is formed over the first epitaxial layer and functions as low ohmic contact to the drain region. In a preferred embodiment both the source and drain regions have dopant concentrations provided by N+ (or P+) doped regions (32, 34) in the surface of a substrate (30) with epitaxial layers thereover. The dopant profile reduces the voltage drop across the more highly doped region of the drain and thereby reduces the electric field therein. Further, the reduction in dopant concentration reduces the electric field due to energy band bending associate with the change in doping level from the N+ (P+) region (46, 48) to the N- (P-) (42, 44) epitaxial layer. The resulting sub-micron device has better long-term reliability. The epitaxial layers are adjacent to and spaced from the gate contact (36) by a dielectric layer (40) such as silicon oxide. In a preferred embodiment (fig. 4C), the dielectric layer (52) is thicker between the second epitaxial layer (46, 48) and the gate contact (36) than between the first epitaxial layer (42, 44) and the gate contact (36).

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