Hot-clock adiabatic gate using multiple clock signals with...

Details Hot-clock adiabatic gate using multiple clock signals with... Hot-clock adiabatic gate using multiple clock signals with...

H - Electricity

03

K

H03K 19/003 (2006.01) H03K 19/00 (2006.01) H03K 19/017 (2006.01) H03K 19/0948 (2006.01) H03K 19/096 (2006.01) H03K 19/20 (2006.01)

Patent

CA 2151850

A hot clock adiabatic gate, using CMOS technology, incorporates an ancillary transistor. The gate is energized by multiple clock signals of different phases to reduce power consumption. The output logic voltage of the gate can reach full-rail voltage by allowing the CMOS technology to discharge via the ancillary transistor. The hot clock adiabatic gate and associated transistor may be incorporated into various logic circuits, such as an inverter, a memory cell, a NAND gate, an AND gate, a NOR gate, or an OR gate. In one configuration, a CMOS inverter is controlled by four clock signals having four discrete phases. The CMOS inverter optimally includes a CMOS gate transistor pair wherein the semiconductor channels of two ancillary transistors are in series with the semiconductor channels of the CMOS gate transistor pair.

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