I/o bus transceiver for a data processing system

Details I/o bus transceiver for a data processing system I/o bus transceiver for a data processing system

G - Physics

06

F

354/233

G06F 13/42 (2006.01) G06F 13/38 (2006.01)

Patent

CA 1075822

I/O BUS TRANSCEIVER FOR A DATA PROCESSING SYSTEM ABSTRACT OF THE DISCLOSURE There is disclosed an input/output system, employed within a data processing system that includes a central processing unit (CPU). The CPU includes improved input/output shift register structure or apparatus for interfacing with and I/means (bus structure). The I/O structure includes improved CPU transceiver and peripheral device transceiver apparatus. The device trans- ceiver interfaces with an improved device controller. In the preferred embodiment of the present invention, the CPU, CPU trans- ceiver, device transceiver, and device controller, all being constructed primarily from MOS technology, are each contained within a respective chip. Further features of the input/output system include capability for placement of multiple transceiver/ controllers and their respective peripheral devices at varying distances from the CPU by virtue of novel clock and data trans- mission means which maintains accurate processing of data regard- less of propagation delay, distortion, data skewing, etc., due to varying transmission distances and inherent limitations of MOS, bipolar, and other technology. -1-

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