I/o controller for multiple disparate serial memories with a...

Details I/o controller for multiple disparate serial memories with a... I/o controller for multiple disparate serial memories with a...

G - Physics

06

F

354/241

G06F 12/08 (2006.01) G06F 13/20 (2006.01)

Patent

CA 1235231

I/O CONTROLLER FOR MULTIPLE DISPARATE SERIAL MEMORIES WITH A CACHE ABSTRACT An I/O controller for disparate serial memories and a cache memory for the controller, comprising a device data flow section with a device bus linking a A buffer RAM through registers to the respective mem- ories and to a buffer register and further comprising a cache bus linking the buffer register to a cache memory and through a channel register to the main processor. Data is transferred from the disks to the buffer register through the buffer RAM. The device and cache data flows can proceed independently.

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