G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 12/00 (2006.01) G06F 12/08 (2006.01) G06F 13/28 (2006.01) G11B 23/00 (2006.01)
Patent
CA 2298780
A special 'I/O' page, is defined as having a large size (e.g., 4K bytes), but with distinctive cache line characteristics. For DMA reads, the first cache line in the I/O page may be accessed, by a PCI Host Bridge, as a cacheable read and all other lines are non- cacheable access (DMA Read with no intent to cache). For DMA writes, the PCI Host Bridge accesses all cache lines as cacheable. The PCI Host Bridge maintains a cache snoop granularity of the I/O page size for data, which means that if the Host Bridge detects a store (invalidate) type system bus operation on any cache line within an I/O page, cached data within that page is invalidated (L1/L2 caches continue to treat all cache lines in this page as cacheable. By defining the first line as cacheable, only one cache line need be invalidated on the system bus by the L1/L2 cache in order to cause invalidation of the whole page of data in the PCI Host Bridge. All stores to the other cache lines in the I/O Page can occur directly in the L1/L2 cache without system bus operations, since these lines have been left in the 'modified' state in the L1/L2 cache.
Anderson Gary Dean
Arroyo Ronald Xavier
Frey Bradly George
Guthrie Guy Lynn
International Business Machines Corporation
Rosen Arnold
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