I/o structure for information processing system

Details I/o structure for information processing system I/o structure for information processing system

G - Physics

06

F

354/236

G06F 13/12 (2006.01)

Patent

CA 1272299

70840-69 ABSTRACT OF THE DISCLOSURE An information processing system includes an internal processor, an internal system bus for communication among the internal processing elements, and peripherals for conducting information into and out of the system. Input/output (1/0) devices are connected from the internal bus and to the peripherals for conducting information among the peripheral elements and the internal elements. A control bus is provided for conducting control words among the peripherals connected from the 1/0 device. Each control word includes a target identification field containing information identifying a peripheral connected from the 1/0 device and a command field containing information identifying a type of 1/0 operation to be executed. An address/data bus is provided for conducting address/data words among the peripherals connected from the 1/0 device. Each communication of an address/data word is accompanied by the communication of a corresponding control word. The execution of an 1/0 operation involves the transmitting at least one address/data word. Each address/ data word includes information to be transferred. The information includes data or a message or address information identifying a destination in the address space of the internal processor of the information to be transferred. With each address/data word there is transmitted a control word. Each control word includes a target identification field containing information identifying a peripheral connected from the 1/0 device and a command field containing information identifying a type of 1/0 operation to be executed.

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