G - Physics – 06 – F
Patent
G - Physics
06
F
354/237
G06F 9/46 (2006.01) G06F 9/48 (2006.01) G06F 13/12 (2006.01) G06F 12/08 (2006.01)
Patent
CA 1306311
ABSTRACT An I/O processor and a memory where a number of queues or linked control blocks (IOCB 1 and IOCB 2) are maintained for each device connected to the I/O processor. There is a control block for every operation to be performed by a particular device. A device may be an I/O bus, a controller unit or a peripheral unit. The I/O processor maintains a table of different combinations of buses and peripheral controllers that may be used to access a given peripheral unit and selects that combination with the least frequency of use. A portion of main memory is assigned as a single cache so that when the I/O processor accesses a data segment in one of may disk drives, the entire disk drive track (59a, b & c) being accessed is read into the assigned cache portion of main memory since following data requests would most likely be made therefrom. The I/O system is provided with a task control processor which provides for the scheduling of the different central processors for the highest priority processes to be run. When an initiate I/O operation is detected, the respective processor is released from the process that it is currently running and can be assigned to the next highest priority process. When the requested I/O operation has been completed, the Task Control Processor is signalled so that the Task Control Processor can put the requesting process back into the priority list of processes to be run by the main central processors.
550970
Missimer David Ross
Murphy Philip Arthur
Peacock Richard Browning
R. William Wray & Associates
Unisys Corporation
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