Ic with means for reducing esd damage

Details Ic with means for reducing esd damage Ic with means for reducing esd damage

H - Electricity

01

L

356/134

H01L 27/04 (2006.01) H01L 23/60 (2006.01) H01L 27/02 (2006.01)

Patent

CA 1303753

ABSTRACT An integrated-circuit (IC) chip having means to prevent or mitigate damage from electrostatic dis- charge (ESD) employing a thick dielectric coating of insulative oxide between the surface of the chip sub- strate and the metallization film used to make contact with regions of the substrate. At least a portion of this layer is formed at temperatures below 700°C. The coating is sufficiently thick everywhere that its break- down voltage is greater than the breakdown voltage of any junction in the substrate. This assures that the break- down caused by ESD will always occur in the junction, which is self healing, rather than in the dielectric coating, where the damage could be permanent.

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