Id generation apparatus and method for serially...

Details Id generation apparatus and method for serially... Id generation apparatus and method for serially...

G - Physics

11

C

G11C 8/18 (2006.01) G11C 8/04 (2006.01) G11C 8/06 (2006.01) G11C 16/02 (2006.01)

Patent

CA 2671184

A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.

Une pluralité de dispositifs mémoires (mémoires DRAM, SRAM, NAND Flash, NOR Flash, par exemple) sont interconnectés en série. Chacun des dispositifs interconnectés reçoit un identifiant (ID) et le verrouille comme étant son identifiant (ID). Chaque dispositif comprend un circuit pour calculer un autre identifiant ou un identifiant incrémenté pour le générer. L'identifiant généré est transféré vers un autre dispositif et l'identifiant est incrémenté dans chacun des dispositifs agencés dans l'interconnexion série. Le dernier dispositif de l'interconnexion fournit un identifiant généré en dernier qui est transféré vers un contrôleur mémoire comprenant un circuit de reconnaissance qui reconnaît le nombre total des dispositifs interconnectés en série à partir de l'identifiant généré en dernier, obtenu. Le circuit de reconnaissance reconnaît le temps de latence total de sortie des dispositifs de l'interconnexion en série.

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