Improved neural semiconductor chip architectures and neural...

Details Improved neural semiconductor chip architectures and neural... Improved neural semiconductor chip architectures and neural...

G - Physics

06

F

G06F 15/80 (2006.01) G06N 3/063 (2006.01)

Patent

CA 2149479

There is disclosed the architecture of a neural semiconductor chip first including a neuron unit comprised of a plurality of neuron circuits fed by different buses transporting data such as the input vector data, set-up parameters, and control signals. Each neuron circuit includes means for generating local result signals of the "fire" type and a local output signal of the distance or category type on respective buses. An OR circuit performs an OR function for all corresponding local result and output signals to generate respective first global result and output signals on respective buses that are merged in an on-chip common communication bus shared by all neuron circuits of the chip. An additional OR function is then performed between all corresponding first global result and output signals to generate second global result and output signals, preferably by dotting on an off-chip common communication bus in the driver block. This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired size. In the chip, a multiplexer may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-back bus. The feedback signal results of a collective processing of all the local signal.

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