Improvements in or relating to real-time pipeline fast...

Details Improvements in or relating to real-time pipeline fast... Improvements in or relating to real-time pipeline fast...

G - Physics

06

F

G06F 17/14 (2006.01)

Patent

CA 2242823

A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-22 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-22 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.

L'invention porte sur un processeur pipeline en temps réel particulièrement adapté à l'architecture VLSI et basé sur un algorithme à base 2?2¿ "orienté matériel" obtenu en intégrant une technique de décomposition en facteurs par retouches selon une approche du type division/recombinaison. L'algorithme à base 2?2¿ présente la même complexité multiplicative qu'un algorithme à base 4, mais conserve la structure en papillon d'un algorithme à base 2. On recourt à une architecture du type monovoie à rétroaction différée permettant d'exploiter la régularité spatiale du graphe de cheminement des signaux de l'algorithme. Pour une TRF de longueur N, le besoin en matériel du processeur de l'invention est minime en ce qui concerne deux composants majeurs: les multiplicateurs Log¿4? N-1 complexes et a mémoire de données N-1 complexes.

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