Improving memory read stability using selective precharge

G - Physics – 11 – C

Patent

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G11C 7/12 (2006.01)

Patent

CA 2709400

A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell (34). A reduction in bit line voltage is achieved by precharging different sections (31, 33) of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference (B2-C2) between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground.

La présente invention concerne un dispositif de mémoire qui utilise la précharge sélective et le partage de la charge pour réduire la tension d'une ligne de bits avant d'accéder à une cellule de bit (34). On obtient une réduction de la tension d'une ligne de bits en préchargeant différentes sections (31, 33) de la ligne de bits à différentes tensions (par exemple, une tension d'alimentation et une terre) et par le partage de la charge entre ces sections. La stabilité de lecture s'améliore du fait de la réduction de la tension de la ligne de bits. La différence de capacité relative (B2-C2) entre les sections de ligne de bits détermine la tension de ligne de bits après le partage de la charge. Le dispositif à mémoire tolère ainsi les variations de traitement ou de température. La configuration de la tension de ligne de bits peut être commandée par la sélection des sections qui sont préchargées à la tension d'alimentation ou à terre.

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