H - Electricity – 04 – B
Patent
H - Electricity
04
B
328/82
H04B 15/00 (2006.01)
Patent
CA 1106002
Abstract of the Disclosure A circuit for limiting impulse noise contained in a signal is disclosed. The circuit comprises a delay circuit connected in parallel with a clamp circuit which is formed of two oppositely directed parallel diodes. When a signal is applied to an input of the parallel connected delay and clamp circuits, the clamp circuit prevents the voltage of the input signal from rising higher than a value (positive or negative) which will cause one of the diodes to conduct. Thus, impulse noise can be re- moved from the input to the delay circuit which provides an output signal essentially noise free and delayed with respect to the original signal.
294664
Nippon Electric Co. Ltd.
Smart & Biggar
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