Information processing system

Details Information processing system Information processing system

G - Physics

06

F

G06F 1/32 (2006.01) G06F 11/14 (2006.01)

Patent

CA 2117391

In the process of returning to a series of processes for returning to a normal operation mode, an I/O address showing a change line status register of the FDC is set to a stored register of the trap logic. When the process returns to the normal operation mode and then an access to the first status register is trapped, a change line status flag value is rewritten. The faked OS/driver invalidates the floppy disk allocation information in the main memory.

Dans une suite de processus de retour à un mode de fonctionnement normal, l'adresse d'entrée-sortie d'un registre d'états de ligne du contrôleur de disquette est versée dans un registre du dispositif logique de piégeage. Quand le processus revient au mode de fonctionnement normal et qu'un accès au premier registre d'états est piégé, une valeur de drapeau d'état de ligne est réinscrite. Le système d'exploitation/pilote simulé invalide l'information d'attribution des disquettes stockée dans la mémoire principale.

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