Input/output arrangement for massively parallel computer system

Details Input/output arrangement for massively parallel computer system Input/output arrangement for massively parallel computer system

G - Physics

06

F

G06F 15/80 (2006.01) G06F 15/173 (2006.01) G06F 11/22 (2006.01)

Patent

CA 2115738

2115738 9304438 PCTABS00020 A computer comprising a plurality of processing elements (11) and an input/output processor (13) interconnected by a routing network (15). The routing network (15) transfers messages between the processing elements (11) and the input/output processor (13). The processing elements (11) perform processing operations in connection with data received from the input/output processor in messages transferred over the routing network and transferring processed data to the input/output processor in messages over the routing network, the processing elements being connected as a first selected series of leaf nodes. The input/output processor includes a plurality of input/output buffers connected as a second selected series of leaf nodes of the routing network for generating messages for transfer over the routing network to a series of processing elements forming at least a selected subset of the processing elements during an input/output operation.

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