Input/output cache system including bypass capability

Details Input/output cache system including bypass capability Input/output cache system including bypass capability

G - Physics

06

F

354/233, 354/237

G06F 13/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1105147

ABSTRACT OF THE DISCLOSURE A local memory of an input/output system includes a cache store and a backing store. The system includes a plurality of command modules. The cache store provides fast access to blocks of information previously fetched from the backing store in response to memory commands generated by any one of a plurality of command modules during both data transfer and data processing operations. Each memory command applied to the memory unit includes a predetermined bit which is coded to designate when the information requested from the local memory unit is to be written into the cache store. The local memory unit includes apparatus operative in response to each memory command to enable the command module to bypass selectively the cache store in accordance with the coding of the predetermined bit thereby enabling the command modules to execute operations more expeditiously during the performance of input/output data transfer operations.

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