H - Electricity – 04 – Q
Patent
H - Electricity
04
Q
344/25, 344/29
H04Q 3/54 (2006.01) H04L 12/56 (2006.01)
Patent
CA 1140239
INPUT-OUTPUT INTERFACE DEVICE BETWEEN A SWITCHING EXCHANGE AND A PLURALITY OF TRANSMISSION CHANNELS ABSTRACT OF THE DISCLOSURE An input-output interface connected between a data switching exchange and a plurality of two-way data transmission channels, for controlling the data frames for each channel. The exchange processes the data in "packets", the data being transmitted on the transmission channels in "frames", each frame containing one or several packets of data, each packet being composed of a plurality of 8-bit bytes. Each data transmission channel is comprised of a data transmission line and a clock transmission line. The interface is comprised of a bit stage that is comprised of a line condition scanner, a timing circuit generating an elementary operation cycle, and a plurality of memories each memory associated with a logic operator able to perform a specific operation. Multiplexers are respectively connected to the reverse direction data transmission lines, and demultiplexers are respectively connected to forward data transmission lines. The scanner cyclically and sequentially scans the clock transmission lines, the scanner cycle being substantially shorter than the shortest duration of a bit transmitted on the channels. Each memory is constituted of as many words as reverse and forward channels, word addresses in each memory being assigned to the scanner position. Each memory together with its operator performs during an elementary operation cycle, a specific operation, such as a register shift for writing a bit from a multiplexer addressed by the scanner and connected to the concerned backward line, or for reading a bit to a demultiplexer addressed by said scanner and connected to the related forward line, or an increment, or any other operation relative to a bit received from a reverse direction line or transmitted to a forward line, and, when the 8th bit of a byte is concerned, relative to that byte. Any condition change by positive transition of any clock transmission line causes the scanner to stop which then triggers the operation of the timing circuit for an elementary operation cycle, and the addressing of the said plurality of memories. Each memory together with its operator performs during the elementary operation cycle the specific operation assigned thereto. At the end of the elementary operation cycle, the scanner resumes scanning.
339656
Cheminel Daniel
Renoulin Roger
Thepaut Bernard
Cheminel Daniel
Etablissement Public de Diffusion Dit "telediffusion de France"
Pascal & Associates
Renoulin Roger
LandOfFree
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