Input register for test operand generation

Details Input register for test operand generation Input register for test operand generation

G - Physics

06

F

328/44, 324/58.1

G06F 7/58 (2006.01) G01R 31/28 (2006.01) G01R 31/3181 (2006.01) G06F 11/26 (2006.01)

Patent

CA 1286371

ABSTRACT Disclosed is an arrangement for a VLSI circuit, comprising an improved input register useful at least for generat- ing sequentially pseudo-random input operands, wherein the in- put register is a serial shift register comprised on a chain of serially shifted flip-flops from first to last having a serially shifted external input to its first flip-flop. When configured to generate such operands, the register comprises a plurality of connected segments of unequal length. The output of the last flip-flop in each segment is fed back into predetermined flip- flops within that segment, such predetermined flip-flops being of a number less than the number of flip-flops in that segment. The feedback is XORed into each such predetermined flip-flop with the output of the flip-flop that precedes the particular pre- determined flip-flop in the chain. The first segment first flip- flop receives the XORed output of the last flip-flop in the first segment XORed with the external input, and the other of the plurality of segments first flip-flops receive their input from the last flip-flops of the just preceding segment XORed with the output from the last flip-flop in their segment.

569945

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