G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.8
G06F 9/40 (2006.01) G06F 9/38 (2006.01) G06F 12/08 (2006.01)
Patent
CA 1132714
ABSTRACT OF THE DISCLOSURE A data processing system comprises a data processing unit coupled to a cache unit which couples to a main store. The cache unit includes a cache store organized into a plurality of levels, each for storing blocks of information in the form of data and instructions. The cache unit further includes an instruction buffer having first and second sections for storing instruc- tions received from main store. Each instruction buffer section includes a plurality of word storage locations, each location having a number of bit positions. A predetermined bit position of each loca- tion is used to indicate when an instruction word has been written into the location. Control apparatus coupled to each of the buffer sections is operative to reset all of the word locations to binary ZEROS when a command requesting an instruction block from main store is ready to be transferred thereto. It is set to a binary ONE state when an instruction word is loaded into the location. Instruction buffer ready circuits included within the control apparatus are conditioned by the states of the predetermined bit positions of the locations to generate output signals to the processing unit enabling the transfer of requested instruction words to the processing unit as soon as they are received from main store.
338605
Norman Robert W. Jr.
Porter Marion G.
Honeywell Information Systems Inc.
Smart & Biggar
LandOfFree
Instruction buffer apparatus of a cache unit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Instruction buffer apparatus of a cache unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Instruction buffer apparatus of a cache unit will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-767147