Instruction prefetch buffer control

Details Instruction prefetch buffer control Instruction prefetch buffer control

G - Physics

06

F

354/230.87

G06F 9/38 (2006.01)

Patent

CA 1242282

ABSTRACT An instruction prefetch buffer control (20) is provided for an instruction prefetch buffer array (10) which stores the code for a number of instructions that have already been executed as well as the code for a number of instructions yet to be executed. The instruction prefetch buffer control includes a register (201) for storing an instruction fetch pointer, this pointer being supplied to the buffer array (10) as a write pointer which points to the location in the array where a new word is to be written from main memory. A second register (205) stores an instruction execution pointer which is supplied to the buffer array (10) as a read pointer. A first adder (203) increments the first register to increment the instruction fetch pointer for sequential instructions and calculates a new instruction fetch pointer for branch instructions. A second adder (215) increments the second register to increment the instruction execution pointer for sequential instructions and calculates a new instruction execution pointer for branch instructions. Incrementing of the second register is variable depending on the length of the instruction. A third adder (221) is responsive to the output of the first adder and a branch target address to calculate whether the target instruction is contained in the array (10) and, if it is, causes the new- instruction execution pointer calculated by the second adder (215) to be loaded into the second register (205).

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