Insulator structure for amorphous silicon thin-film transistors

Details Insulator structure for amorphous silicon thin-film transistors Insulator structure for amorphous silicon thin-film transistors

G - Physics

02

F

356/149, 345/8

G02F 1/133 (2006.01) C09K 19/00 (2006.01)

Patent

CA 2021079

RD-19,360 IMPROVED INSULATOR STRUCTURE FOR AMORPHOUS SILICON THIN-FILM TRANSISTORS A thin-film field-effect-transistor (TFT) includes a gate electrode disposed on a substrate; a first thick layer of silicon nitride is disposed on the substrate and over the gate electrode and a second thinner layer of silicon nitride is disposed on the first layer. The first silicon nitride layer has a silicon-to-nitrogen concentration ratio selected to provide optimum structural characteristics, such as high density, high dielectric strength, low etch rate and the like, to the resulting TFT while the second silicon nitride layer has a silicon-to-nitrogen concentration ratio selected to provide a good electrical interface between the first silicon nitride layer and a subsequently deposited first layer of amorphous silicon. Another layer of doped amorphous silicon is formed on the first amorphous silicon layer and the second doped layer is patterned to form source and drain regions of the TFT. A source electrode and a drain electrode are respectively disposed in contact with the source and drain regions.

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