Integrated circuit and method for fabrication thereof

Details Integrated circuit and method for fabrication thereof Integrated circuit and method for fabrication thereof

H - Electricity

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L

356/153

H01L 27/10 (2006.01) H01L 21/78 (2006.01) H01L 27/00 (2006.01) H01L 27/02 (2006.01) H01L 27/07 (2006.01) H01L 27/082 (2006.01)

Patent

CA 1044817

IMPROVED INTEGRATED CIRCUIT AND METHOD FOR FABRICATION THEREOF Abstract of the Disclosure An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in a N-type epitaxial layer over- lying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the coll- ector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

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