Integrated circuit chip wiring arrangement providing reduced...

Details Integrated circuit chip wiring arrangement providing reduced... Integrated circuit chip wiring arrangement providing reduced...

H - Electricity

01

L

356/30

H01L 23/50 (2006.01) H01L 23/528 (2006.01) H01L 27/04 (2006.01) H01L 27/112 (2006.01)

Patent

CA 1223670

ABSTRACT OF THE DISCLOSURE The area circumscribed by the current path on an integrated circuit chip is diminished, to thereby reduce the inductance of the chip and the likelihood of inductively generated errors, by disposing the bonding pads, through which the current source and current sink are respectively connected to logic gates, physically adjacent to one another. A further reduction in the area of the current loop is obtained by locating power and ground busses adjacent to one another relative to the logic gates. These two busses can be superposed one over the other on different metallic layers of the chip, so that the space between them is only the thickness of the isolation layer which separates the two metallic layers. The distribution of voltage to the logic gates is made uniform by varying the widths of the busses along their lengths in accordance with the currents they carry, and by ensuring that the total length of the current path for the gates is the same for every gate.

462640

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